Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a substrate. A network of signal paths is normally routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. Within a typical network of signal paths, metal vias (e.g., studs) run substantially perpendicular to the top surface of the substrate and metal lines (e.g., wires, interconnects) run substantially parallel to the top surface of the substrate.
The interface where a via lands on a wire (interconnect) is susceptible to stress migration failure characterized by voids (vacancies) that form in the conductive material. Stress migration failure in a copper (Cu) interconnect is problematic due to the fast diffusing interface between the Cu wire and the nitride capping layer over the wire. As vacancies in the Cu diffuse, they move to the Cu/nitride interface and diffuse to the wire-to-via interface. An accumulation of such vacancies can result in an open connection, which results in a lack of electrical conduction and failure of the circuit. Since there is typically no redundant path between the top of the Cu wire and the via, a small amount of voiding can lead to a failed connection. In fact, a slit void is sufficient in most cases to lead to circuit failure.
An approach to addressing the stress migration failure in general is to utilize a silicon-rich copper-to-nitride interface to slow the vacancy diffusion. However, this approach disadvantageously causes unwanted variability of the metal resistance (Rs). Moreover, this approach ignores the via-to-wire interface as the fail location.
Another approach to addressing the stress migration failure in general is to dope a Cu seed layer to reduce vacancy diffusion. For example, a copper-manganese (CuMn) layer may be formed on top of the Cu wire. However, this approach disadvantageously causes unwanted loss of metal resistance (Rs). Moreover, this approach ignores the via-to-wire interface as the fail location.
An approach to addressing the stress migration failure at the via-to-wire interface is to employ via liner re-sputtering to gouge the Cu wire. This ensures a tantalum (Ta) to Cu interface which advantageously avoids nitrides at the Cu interface. However, this approach disadvantageously induces sputter damage into the Cu wire, which pre-disposes vacancy sites at the via-to-wire interface.
Another approach to addressing the stress migration failure at the via-to-wire interface is to provide the Cu wire with capping layers, such as cobalt tungsten phosphide (CoWP) or tantalum/tantalum nitride (Ta/TaN). For example, a redundant layer may be added to the top surface of the Cu wire after a chemical mechanical polish (CMP) of the Cu wire. The layer may comprise CoWP; however, CoWP is selective and expensive to process. The layer may comprise Ta/TaN; however, this requires an additional mask level to the etch cap and results in overlay and leakage penalties.
Other approaches include using a TaN/TiN or a Ti/TiN/Ti liner with the via. Using a TaN/TiN liner places a nitride material directly on the Cu wire, which results in the same problem as the nitride capping layer in the first place, i.e., a fast diffusing interface between the Cu wire and the nitride capping layer over the wire. Using a Ti/TiN/Ti liner typically results in nitrogen poisoning of the Ti liner, which disadvantageously results in the presence of the nitrogen at the Cu interface and thus induces adhesion problems associated with Cu and metal nitrides.